Semiconductor device

ABSTRACT

A semiconductor device is disclosed that includes a plurality of isolation regions. A fin is arranged between the plurality of isolation regions. One of the plurality of isolation regions includes a first atomic layer deposition (ALD) layer, a second ALD layer, a flowable chemical vapor deposition (FCVD) layer, and a third ALD layer. The first ALD layer includes a first trench. The second ALD layer is formed in the first trench of the first ALD layer. The FCVD layer is formed in the first trench of the first ALD layer and on the second ALD layer. The third ALD layer is formed on the FCVD layer.

RELATED APPLICATIONS

This application claims priority to U.S. Provisional Application Ser. No. 62/592,852, filed Nov. 30, 2017, which is herein incorporated by reference.

BACKGROUND

Isolation structures such as dummy fins are used for isolating fins in semiconductor structures. However, when the dummy fins are formed, in some conditions, the quality of the dummy fins is poor, which results in deteriorating the dummy fins during wet or dry processes.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic diagram of a semiconductor device, in accordance with some embodiments of the present disclosure.

FIGS. 2-13 are process flows for manufacturing the semiconductor device in FIG. 1, in accordance with some embodiments of the present disclosure.

FIG. 14 is a schematic diagram of a semiconductor device, in accordance with some other embodiments of the present disclosure.

FIGS. 15-17 are front views of the semiconductor device in FIG. 14, in accordance with some embodiments of the present disclosure.

FIGS. 18-31 are process flows for manufacturing the semiconductor device in FIG. 14, in accordance with some embodiments of the present disclosure.

FIG. 32 is a schematic diagram of a semiconductor device, in accordance with various embodiments of the present disclosure.

FIGS. 33-35 are front views of the semiconductor device in FIG. 32, in accordance with some embodiments of the present disclosure.

FIGS. 36-49 are process flows for manufacturing the semiconductor device in FIG. 32, in accordance with some embodiments of the present disclosure.

FIG. 50 is a schematic diagram of a semiconductor device, in accordance with alternative embodiments of the present disclosure.

FIGS. 51-61 are process flows for manufacturing the semiconductor device in FIG. 50, in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Reference is made to FIG. 1. FIG. 1 is a schematic diagram of a semiconductor device 1000, in accordance with some embodiments of the present disclosure.

As illustratively shown in FIG. 1, the semiconductor device 1000 includes isolation regions 1100, 1200, 1300. Fins 1600, 1700 are arranged between the plurality of isolation regions 1100, 1200, 1300. For illustration, the fin 1600 is arranged between the isolation regions 1100, 1200, and the fin 1700 is arranged between the isolation regions 1200, 1300. In various embodiments, the plurality of isolation regions 1100, 1200, 1300 are used as dummy fins.

In various embodiments, one of the plurality of isolation regions, for example, the isolation region 1100, includes a first atomic layer deposition (ALD) layer 1110, a second ALD layer 1120, a flowable chemical vapor deposition (FCVD) layer 1130, and a third ALD layer 1140. The first ALD layer 1110 includes a first trench 1112. The second ALD layer 1120 is formed in the first trench 1112 of the first ALD layer 1110. The FCVD layer 1130 is formed in the first trench 1112 of the first ALD layer 1110 and on the second ALD layer 1120. The third ALD layer 1140 is formed on the FCVD layer 1130.

In some embodiments, the third ALD layer 1140 is also formed in the first trench 1112 of the first ALD layer 1110 and on the FCVD layer 1130. In various embodiments, the third ALD layer 1140 is in contact with the second ALD layer 1120 and the FCVD layer 1130.

In various embodiments, the first ALD layer 1110 includes a first opening 1114, and the second ALD layer 1120 includes a second opening 1122. The first opening 1114 and the second opening 1122 are disposed at the same side, for example, the upper side of the semiconductor device 1000 as illustrated in FIG. 1. In some embodiments, the third ALD layer 1140 covers the second opening 1122 of the second ALD layer 1120. In various embodiments, the third ALD layer 1140 is in contact with the second ALD layer 1120 and the FCVD layer 1130.

In some embodiments, one of the plurality of isolation regions, for example, the isolation region 1200, includes a fourth ALD layer 1210 and a fifth ALD layer 1220. The fourth ALD layer 1210 includes a second trench 1212. The fifth ALD layer 1220 is formed in the second trench 1212 of the fourth ALD layer 1210.

In various embodiments, a width of one of the plurality of isolation regions is larger than a width of another one of the plurality of isolation regions. For illustration in FIG. 1, the width W1 of the isolation region 1100 is larger than the width W2 of the isolation region 1200. For another illustration, the width W2 of the isolation region 1200 is larger than the width W3 of the isolation region 1300. The widths of the isolation regions in the semiconductor device 1000 described above is given for illustrative purposes. Various widths of the isolation regions in the semiconductor device 1000 are within the contemplated scope of the present disclosure.

In various embodiments, the materials of the first ALD layer 1110 and the third ALD layer 1140 are selected from a group consisting of SiOC, SiOCN, and metal oxide such as HfO2, ZrO2. The material of the second ALD layer 1120 is selected from a group consisting of SiN, SiCN, and SiOCN. The materials of the ALD layers described above are given for illustrative purposes. Various materials of the ALD layers are within the contemplated scope of the present disclosure.

In some approaches, quality of FCVD layers in isolation regions are poor, and the FCVD layers would result in loss of the dummy fins during wet or dry processes.

Compared to the approaches above, in the present disclosure, the FCVD layer 1130 of the isolation region 1100 is surrounded by the second ALD layer 1120 and the third ALD layer 1140. Moreover, the first ALD layer 1110 further surrounds the FCVD layer 1130, the second ALD layer 1120 and the third ALD layer 1140. Accordingly, the FCVD layer 1130 is protected by the first ALD layer 1110, the second ALD layer 1120 and the third ALD layer 1140.

The structure of the semiconductor device 1000 described above is given for illustrative purposes. Various structures of the semiconductor device 1000 are within the contemplated scope of the present disclosure.

FIGS. 2-13 are process flows of manufacturing the semiconductor device 1000 in FIG. 1, in accordance with some embodiments of the present disclosure.

As illustratively shown in FIG. 2, a plurality of fins 1500, 1600, 1700, 1800, 1900 are formed by etching process, and an oxide layer O1 is formed on the fins 1500, 1600, 1700, 1800, 1900. With the formation of the fins 1500, 1600, 1700, 1800, 1900 and the oxide layer O1, a trench T1 is formed accordingly.

The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

With reference to FIG. 3, an ALD material A1, used as an oxide spacer, is formed on the oxide layer O1, and disposed over the fins 1500, 1600, 1700, 1800, 1900. The ALD layer 1300 as a dummy fin is therefore formed in the trench T1 as shown in FIG. 2.

As illustratively shown in FIG. 4, coarse cut etching is performed to the fins 1500, 1600, 1700, 1800, 1900, the oxide layer O1 and the ALD material A1, and a new trench T2 is formed. Reference is made to FIG. 5, an ALD material A2 as Chemical-Mechanical Polishing (CMP) stop layer or etching stop layer is formed on the structure in FIG. 4. The ALD layer 1220 as a dummy fin is therefore formed in the trench T3 as shown in FIG. 4.

Reference is made to FIG. 6, a FCVD layer F1 is formed on the structure in FIG. 5 first, and a CMP process is performed to the formed structure afterwards. Since the ALD material A2 is used as a CMP stop layer, the FCVD layer F1 is polished and stopped at the ALD material A2. Accordingly, the FCVD layer F1 fills in the trench T2 and the trench T5 as shown in FIG. 5. In FIG. 7, an oxide recess process is preformed to recess the FCVD layer Fl, and the upper portion of the FCVD layer F1 is removed. Subsequently, an ALD material A3 is formed on the recessed structure as mentioned above, and an oxide layer O2 is formed on the ALD material A3.

As illustratively shown in FIG. 8, a CMP process is performed. The oxide layer O2 is therefore removed, and the upper portions of the oxide layer O1, the ALD layers A1, A2, A3 are also removed. Referring to FIG. 9, a Shallow Trench Isolation (STI) recess process is performed. The upper portion of the oxide layer O1 is removed, and the fin structures such as the fins 1500-1900 and the isolation regions 1100, 1200, 1300 as dummy fins are therefore formed.

With reference to FIG. 10, a dummy oxide layer O3 as a gate dielectric layer is disposed on the fins 1500-1900 and the isolation regions 1100-1300 as dummy fins, and a poly layer used for forming poly patterns P1 is disposed on the dummy oxide layer O3. Subsequently, photo resists R1 and hard masks H1 are disposed on the poly layer for forming poly patterns P1, and a poly patterning process is preformed, in order to form the poly patterns P1 as shown in FIG. 10. In FIG. 11, spacers 51 are formed on the side walls of the poly patterns P1, and a fin side wall pull back (FSWPB) process is performed to pull back the dummy oxide layer O3 as shown in FIG. 10. In addition, a source/drain (S/D) epi process is performed to form helmet-shaped structures H2 on the S/D.

As illustratively shown in FIG. 12, a dielectric layer D1 is disposed on the structure as shown in FIG. 11. Subsequently, a CMP process is performed to remove the photo resists R1, the hard masks H1, and the upper portion of the dielectric layer Dl. In addition, a replacement polysilicon gate loop process is performed to replace the poly patterns P1 in FIG. 11 and form metal gates G1 in FIG. 12. In FIG. 13, a cut metal gate (CMG) process is performed to cut a part of the metal gates, and form gate isolations I1. Subsequently, an S/D contact formation process is performed to form S/D contacts M1. In some embodiments, the S/D contact formation process is also referred to as an MD formation process.

Reference is made to FIGS. 14, 15. FIG. 14 is a schematic diagram of a semiconductor device 1000A, in accordance with some embodiments. FIG. 15 is a front view of the semiconductor device 1000A in FIG. 14 from direction D, in accordance with some embodiments of the present disclosure.

As illustratively shown in FIGS. 14, 15, the semiconductor device 1000A includes a first isolation region 1100A, a second isolation region 1200A, and at least one fin (i.e., a fin 1600A). The first isolation region 1100A includes a first ALD layer 1110A, a second ALD layer 1120A, a FCVD layer 1130A, and a deposition layer 1140A. The first ALD layer 1110A includes a first trench 1112A. The second ALD layer 1120A is formed in the first trench 1112A of the first ALD layer 1110A. The FCVD layer 1130A is formed in the first trench 1112A of the first ALD layer 1110A and on the second ALD layer 1120A. In various embodiments, the plurality of isolation regions 1100A, 1200A are used as dummy fins.

For further illustration in FIGS. 14, 15, the second isolation region 1200A includes a third ALD layer 1210A and a fourth ALD layer 1220A. The third ALD layer 1210A includes a second trench 1212A. The fourth ALD layer 1220A is formed in the second trench 1212A of the third ALD layer 1210A. The fin 1600A is arranged between the first isolation region 1100A and the second isolation region 1200A.

In some embodiments, the deposition layer 1140A is formed in the first trench 1112A of the first ALD layer 1110A. In various embodiments, the deposition layer 1140A is in contact with the first ALD layer 1110A, the second ALD layer 1120A, and the FCVD layer 1130A.

In various embodiments, the deposition layer 1140A is an ALD layer. In some embodiments, the second isolation region 1200A includes a fifth ALD layer 1230A, and the fifth ALD layer 1230A is formed in the second trench 1212A and on the fourth ALD layer 1220A.

In various embodiments, the materials of the first ALD layer 1110A and the third ALD layer 1140A are selected from a group consisting of SiOC, SiOCN, and metal oxide such as HfO2, ZrO2. The material of the second ALD layer 1120A is selected from a group consisting of SiN, SiCN, and SiOCN. The materials of the ALD layers described above are given for illustrative purposes. Various materials of the ALD layers are within the contemplated scope of the present disclosure.

As illustratively shown in FIG. 15, a void 1410A is formed between the fins 1800A, 1900A of the semiconductor device 1000A. The void 1410A is formed during the spacer 1420A being merged because the fins 1800A, 1900A are too close to each other. Explained in another way, voids or seams tend to be formed in dense fins such as fins 1800A, 1900A.

FIG. 16 is a front view of the semiconductor device 1000A in FIG. 14 from direction D, in accordance with some embodiments of the present disclosure. Compared with the semiconductor device 1000A in FIG. 15, the deposition layer 1140A of the semiconductor device 1000A herein is different. As illustratively shown in FIG. 16, the deposition layer 1140A includes bumps 1142A, 1144A. The bump 1142A is disposed at the left side of the deposition layer 1140A, and the bump 1144A is disposed at the right side of the deposition layer 1140A. The bumps 1142A, 1144A all extend beyond the button of the deposition layer 1140A.

FIG. 17 is a front view of the semiconductor device 1000A in FIG. 14 from direction D, in accordance with some embodiments of the present disclosure. Compared with the semiconductor device 1000A in FIG. 15, the deposition layer 1140A of the semiconductor device 1000A herein is different. As illustratively shown in FIG. 17, the deposition layer 1140A includes a bump 1146A. The bump 1146A is disposed at the middle of the deposition layer 1140A, and extends beyond the button of the deposition layer 1140A.

FIGS. 18-31 are process flows for manufacturing the semiconductor device 1000A in FIG. 14, in accordance with some embodiments of the present disclosure.

As illustratively shown in FIGS. 18-22, since the processes thereof are similar to the processes in FIGS. 2-6, the detailed description regarding the processes is therefore omitted for the sake of brevity.

Reference is made to FIG. 23, an oxide recess process is preformed to recess the FCVD layer F1, and the upper portion of the FCVD layer F1 is removed. In FIG. 24, an oxide recess process is preformed to recess the ALD material A2. In some embodiments, the ALD material A2 is partially recessed, and part of ALD material A2 remain. For example, the ALD material A21 remains in the trench T6, and the ALD material A22 remains in the trench T7. In various embodiments, the height of the ALD material A22 is the same as that of the FCVD layer F1.

As illustratively shown in FIG. 25, an ALD material A3 is formed on the recessed structure as shown in FIG. 24. Subsequently, an oxide layer O2 is formed on the ALD material A3. In some embodiments, the oxide layer O2 is a plasma enhanced oxide (PEOX) layer. Reference is made to FIG. 26, a CMP process is performed. The oxide layer O2 is therefore removed, and the upper portions of the oxide layer O1, the ALD layers A1, A3 are also removed. Referring to FIG. 27, a STI recess is performed. The upper portion of the oxide layer O1 is removed, and the fin structures such as the fins 1500A-1900A and the isolation regions 1100A, 1200A, 1300A as dummy fins are therefore formed.

Reference is made to FIGS. 28-31, since the processes thereof are similar to the processes in FIGS. 10-13, the detailed description regarding the processes is therefore omitted for the sake of brevity.

Reference is made to FIGS. 32, 33. FIG. 32 is a schematic diagram of a semiconductor device 1000B, in accordance with some embodiments. FIG. 33 is a front view of the semiconductor device 1000B in FIG. 32 from direction D, in accordance with some embodiments of the present disclosure.

Compared the semiconductor device 1000A in FIGS. 14, 15 with the semiconductor device 1000B in FIGS. 32, 33, the semiconductor device 1000A in FIGS. 14, 15 further includes the fifth ALD layer 1230A which is formed in the second trench 1212A and on the fourth ALD layer 1220A. In addition, the deposition layer 1140B of the semiconductor device 1000B in FIGS. 32, 33 is a FCVD layer rather than an ALD layer.

In some embodiments, the FCVD layer 1140B is implanted with impurity. In various embodiments, the FCVD layer 1140B is implanted with high dose impurity. The impurity is selected form a group consisting of Si, Ge, C, Al, and a combination thereof. The impurity is distributed in the FCVD layer 1140B in a gauss manner. In some embodiments, the materials of the first ALD layer 1110B, the third ALD layer 1210B, and the third isolation region 1300B are selected form a group consisting of SiOC, SiOCN, and metal oxide such as HfO2, ZrO2. The materials of the second ALD layer 1120B and the fourth ALD layer 1220B are selected from a group consisting of SiN, SiCN, and SiOCN. The impurity implanted in the FCVD layer 1140B and materials of the ALD layers described above are given for illustrative purposes. Various impurity and materials adopted in the FCVD layer and the ALD layers are within the contemplated scope of the present disclosure.

As illustratively shown in FIG. 33, a curve line 1148B represents a concentration distribution in the deposition layer 1140B of the semiconductor device 1000B. Referring to the curve line 1148B shown in FIG. 33, the middle part of the deposition layer 1140B has the highest concentration, and the concentration is decreased from the middle part to the edge of the deposition layer 1140B in a gauss manner.

Referring to FIG. 33, a void 1410B is formed between the fins 1800B, 1900B of the semiconductor device 1000B. The void 1410B is formed during the spacer 1420B being merged because the fins 1800B, 1900B are close to each other. Explained in another way, voids or seams tend to form in dense fins such as fins 1800B, 1900B.

In some approaches, poor quality of FCVD layers as a dummy fin would induce loss of the dummy fins during wet or dry processes. Compared to the approaches above, in the present disclosure, the FCVD layer 1140B is implanted with high dose impurity such as Si, Ge, C, Al, which largely changes material property of the FCVD layer 1140B as a dummy fin so as to increases wet clean and STI recess certas resistance.

FIG. 34 is a front view of the semiconductor device 1000B in FIG. 32 from direction D, in accordance with some embodiments of the present disclosure. Compared with the semiconductor device 1000B in FIG. 33, the deposition layer 1140B of the semiconductor device 1000B herein is different. As illustratively shown in FIG. 34, the deposition layer 1140B includes bumps 1142B, 1144B. The bump 1142B is disposed at the left side of the deposition layer 1140B, and the bump 1144B is disposed at the right side of the deposition layer 1140B. The bumps 1142B, 1144B all extend beyond the button of the deposition layer 1140B.

FIG. 35 is a front view of the semiconductor device 1000B in FIG. 32 from direction D, in accordance with some embodiments of the present disclosure. Compared with the semiconductor device 1000B in FIG. 33, the deposition layer 1140B of the semiconductor device 1000B herein is different. As illustratively shown in FIG. 35, the deposition layer 1140B includes a bump 1146B. The bump 1146B is disposed at the middle of the deposition layer 1140B and extends beyond the button of the deposition layer 1140B.

FIGS. 36-49 are process flows for manufacturing the semiconductor device 1000B in FIG. 32, in accordance with some embodiments of the present disclosure.

As illustratively shown in FIGS. 36-41, since the processes thereof are similar to the processes in FIGS. 18-23, the detailed description regarding the processes is therefore omitted for the sake of brevity.

Reference is made to FIG. 42, the upper portions of the ALD layers A1, A2, the oxide layer O1, and the FCVD layer F1 are implanted with high dose impurity. In some embodiments, the impurity is selected form a group consisting of Si, Ge, C, Al, and a combination thereof. As illustratively shown in FIG. 43, an ALD material A3 is disposed on the implanted structure as shown in FIG. 42, and an oxide layer O2 is formed on the ALD material A3 thereafter.

As illustratively shown in FIGS. 44-49, since the processes thereof are similar to the processes in FIGS. 26-31, the detailed description regarding the processes is therefore omitted for the sake of brevity.

Reference is made to FIG. 50. FIG. 50 is a schematic diagram of a semiconductor device 2000, in accordance with some embodiments.

As illustratively shown in FIG. 50, the semiconductor device 2000 includes a plurality of fins 2500, 2600, 2700, 2800, 2900, and a plurality of isolation regions 2100A, 2100B, 2200, 2300. Each of the plurality of isolation regions 2100A, 2100B, 2200, 2300 is formed between two of the plurality of fins 2500, 2600, 2700, 2800, 2900. In some embodiments, the plurality of fins 2500, 2600, 2700, 2800, 2900 are adjacent to each other. For example, the fin 2500 is adjacent to the fin 2600, the fin 2600 is adjacent to the fin 2700, and the fin 2700 is adjacent to the fin 2800, and so on.

The first isolation region 2100A of the plurality of isolation regions includes a first ALD layer 2110A and a second ALD layer 2120A. The first ALD layer 2110A includes a first trench 2112A. The first trench 2112A of the first ALD layer 2110A is filled up with the second ALD layer 2120A. The first ALD layer 2110A and the second ALD layer 2120A are implanted with carbon (C) and nitrogen (N) respectively. A concentration which carbon implanted in the second ALD layer 2120A is higher than a concentration which carbon implanted in the first ALD layer 2110A, and a concentration which nitrogen implanted in the second ALD layer 2120A is substantially higher than a concentration which nitrogen implanted in the first ALD layer 2110A.

In some embodiments, the concentration which carbon implanted in the first ALD layer 2110A is about 1-3%, and the concentration which nitrogen implanted in the first ALD layer 2110A is about 5-20%. In various embodiments, the concentration which carbon implanted in the second ALD layer 2120A is about 5-15%, and the concentration which nitrogen implanted in the second ALD layer 2120A is about 10-30%. The concentration which elements implanted in the layers described above is given for illustrative purposes. Various concentrations which elements implanted in the layers are within the contemplated scope of the present disclosure.

In various embodiments, the structure of an isolation region 2100B of the plurality of isolation regions is the similar to the structure of the first isolation region 2100A of the plurality of isolation regions. The difference between the isolation region 2100A and the isolation region 2100B is that the width W2 of the isolation region 2100B is larger than the width W1 of the isolation region 2100A. The difference of the widths of the isolation regions described above is given for illustrative purposes. Various differences of the widths of the isolation regions are within the contemplated scope of the present disclosure.

In some embodiments, the second isolation region 2200 of the plurality of isolation regions includes a third ALD layer 2210, a fourth ALD layer 2220, and a first FCVD layer 2230. The third ALD layer 2210 includes a second trench 2212. The fourth ALD layer 2220 is formed in the second trench 2212 of the third ALD layer 2210. The FCVD layer 2230 is formed in the second trench 2212 of the third ALD layer 2210 and on the fourth ALD layer 2220.

The third ALD layer 2210 and the fourth ALD layer 2220 are implanted with carbon (C) and nitrogen (N). A concentration which carbon implanted in the fourth ALD layer 2220 is higher than a concentration which carbon implanted in the third ALD layer 2210, and a concentration which nitrogen implanted in the fourth ALD layer 2220 is higher than a concentration which nitrogen implanted in the third ALD layer 2210.

In various embodiments, the third isolation region 2300 of the plurality of isolation regions includes a fifth ALD layer 2310, a sixth ALD layer 2320, a second FCVD layer 2330, and a seventh ALD layer 2340. The fifth ALD layer 2310 includes a third trench 2312. The sixth ALD layer 2320 is formed in the third trench 2312 of the fifth ALD layer 2310, and the sixth ALD layer 2320 includes a fourth trench 2322. The second FCVD layer 2330 is formed in the fourth trench 2322 of the sixth ALD layer 2320. The seventh ALD layer 2340 is formed on the second FCVD layer 2330.

The fifth ALD layer 2310, the sixth ALD layer 2320, and the seventh ALD layer 2340 are implanted with carbon (C) and nitrogen (N). A concentration which carbon implanted in the sixth ALD layer 2320 and the seventh ALD layer 2340 are higher than a concentration which carbon implanted in the fifth ALD layer 2310, and a concentration which nitrogen implanted in the sixth ALD layer 2320 and the seventh ALD layer 2340 is higher than a concentration which nitrogen implanted in the fifth ALD layer 2310.

In some approaches, ALD layers as an oxide spacer are needed in semiconductor device to define dummy fin width. However, it is suffered from fin bonding and spacer merge seam issues.

Compared to the approaches above, in the present disclosure, the ALD layers with carbon (C) and nitrogen (N) doping in the semiconductor 2000 achieve better fin bonding and spacer merge seam performance. In addition, the ALD layers with carbon (C) and nitrogen (N) doping is by Si—C—ON bonding, and such bonding leads to better stability.

FIGS. 51-61 are process flows for manufacturing the semiconductor device 2000 in FIG. 50, in accordance with some embodiments of the present disclosure.

As illustratively shown in FIG. 51, a plurality of fins 2500, 2600, 2700, 2800, 2900 are formed by etching process, and an ALD material A1 as a spacer is formed on the fins 2500, 2600, 2700, 2800, 2900. Reference is made to FIG. 52, coarse cut etching is performed to the fins 2500, 2600, 2700, 2800, 2900 and the ALD material A1, and a new trench T1 is formed.

Referring to FIG. 53, an ALD material A2 is formed on the structure as shown in FIG. 52. The ALD layers 2100A, 2100B as dummy fins are therefore formed. In FIG. 54, a FCVD layer F1 is formed on the structure in FIG. 53 first, and a CMP process is performed thereafter. The FCVD layer F1 is polished and stopped at the ALD material A2; and therefore, the FCVD layer F1 fills up the trench T2 as shown in FIG. 53.

As illustratively shown in FIG. 55, an etching process is performed to etch the FCVD F1, and a trench T3 is formed. In FIG. 56, an ALD material A3 fills up the trench T3 as shown in FIG. 55, and an oxide layer O1 is formed on the ALD material A3. In some embodiments, the oxide layer O1 is a PEOX layer.

Reference is made to FIGS. 57-61, since the processes thereof are similar to the processes in FIGS. 26-31, the detailed description regarding the processes is therefore omitted for the sake of brevity. However, there are some differences in the processes, which are described below. In FIG. 58, due to the structure difference, the STI process is performed to remove the upper portion of the ALD material A1 rather than the oxide layer O1 in FIG. 27. Referring to FIG. 60, the shapes of the source/drain (S/D) epi are diamond rather than helmet in FIG. 29.

In some embodiments, a semiconductor device is disclosed that includes a plurality of isolation regions. A fin is arranged between two of the plurality of isolation regions. One of the plurality of isolation regions includes a first atomic layer deposition (ALD) layer, a second ALD layer, a flowable chemical vapor deposition (FCVD) layer, and a third ALD layer. The first ALD layer includes a first trench. The second ALD layer is formed in the first trench of the first ALD layer. The FCVD layer is formed in the first trench of the first ALD layer and on the second ALD layer. The third ALD layer is formed on the FCVD layer.

In some embodiments, the third ALD layer is formed in the first trench of the first ALD layer and on the FCVD layer.

In various embodiments, the third ALD layer is in contact with the second ALD layer and the FCVD layer.

In some embodiments, the first ALD layer includes a first opening, and the second ALD layer includes a second opening, wherein the first opening and the second opening are disposed at the same side of the semiconductor device.

In various embodiments, the third ALD layer covers the second opening of the second ALD layer, and the FCVD layer is surrounded by the second ALD layer and the third ALD layer.

In some embodiments, another one of the plurality of isolation regions includes a fourth ALD layer and a fifth ALD layer. The fourth ALD layer includes a second trench. The fifth ALD layer is formed in the second trench of the fourth ALD layer.

In various embodiments, a width of the one of the plurality of isolation regions is larger than a width of the another one of the plurality of isolation regions.

Also disclosed is a semiconductor device that includes a first isolation region, a second isolation region, and at least one fin. The first isolation region includes a first ALD layer, a second ALD layer, a FCVD layer, and a deposition layer. The first ALD layer includes a first trench. The second ALD layer is formed in the first trench of the first ALD layer. The FCVD layer is formed in the first trench of the first ALD layer and on the second ALD layer. The deposition layer is formed on the second ALD layer and the FCVD layer. The second isolation region includes a third ALD layer and a fourth ALD layer. The third ALD layer includes a second trench. The fourth ALD layer is formed in the second trench of the third ALD layer. The at least one fin is arranged between the first isolation region and the second isolation region.

In some embodiments, the deposition layer is formed in the first trench of the first ALD layer.

In various embodiments, the deposition layer is in contact with the first ALD layer, the second ALD layer, and the FCVD layer.

In some embodiments, the deposition layer comprises an ALD layer, and the FCVD layer is surrounded by the second ALD layer and the deposition layer.

In various embodiments, the second isolation region includes a fifth ALD layer. The fifth ALD layer is formed in the second trench and on the fourth ALD layer.

In some embodiments, the deposition layer is a FCVD layer.

In various embodiments, the deposition layer is implanted with impurity, and the impurity is distributed in the deposition layer in a gauss manner.

In some embodiments, a number of the at least one fin comprises plural, and the semiconductor device further comprises a void. The void is formed between two fins which are adjacent to each other.

Also disclosed is a semiconductor device that includes a plurality of fins and a plurality of isolation regions. Each of the plurality of isolation regions is formed between two of the plurality of fins being adjacent to each other. A first isolation region of the plurality of isolation regions includes a first ALD layer and a second ALD layer. The first ALD layer includes a first trench. The first trench of the first ALD layer is filled with the second ALD layer. The first ALD layer and the second ALD layer are implanted with carbon and nitrogen, wherein a concentration which carbon implanted in the second ALD layer is higher than a concentration which carbon implanted in the first ALD layer, and a concentration which nitrogen implanted in the second ALD layer is higher than a concentration which nitrogen implanted in the first ALD layer.

In some embodiments, the concentration of carbon implanted in the first ALD layer is about 1-3%, and the concentration of nitrogen implanted in the first ALD layer is about 5-20%.

In various embodiments, the concentration of carbon implanted in the second ALD layer is about 5-15%, and the concentration of nitrogen implanted in the second ALD layer is about 10-30%.

In some embodiments, a second isolation region of the plurality of isolation regions includes a third ALD layer, a fourth ALD layer, and a first FCVD layer. The third ALD layer includes a second trench. The fourth ALD layer is formed in the second trench of the third ALD layer. The first FCVD layer is formed in the second trench of the third ALD layer and on the fourth ALD layer. The third ALD layer and the fourth ALD layer are implanted with carbon and nitrogen, wherein a concentration which carbon implanted in the fourth ALD layer is higher than a concentration which carbon implanted in the third ALD layer, and a concentration which nitrogen implanted in the fourth ALD layer is higher than a concentration which nitrogen implanted in the third ALD layer.

In various embodiments, a third isolation region of the plurality of isolation regions includes a fifth ALD layer, a sixth ALD layer, a second FCVD layer, and a seventh ALD layer. The fifth ALD layer includes a third trench. The sixth ALD layer is formed in the third trench of the fifth ALD layer. The sixth ALD layer includes a fourth trench. The second FCVD layer is formed in the fourth trench of the sixth ALD layer. The seventh ALD layer is formed on the second FCVD layer. The fifth ALD layer, the sixth ALD layer, and the seventh ALD layer are implanted with carbon and nitrogen, wherein a concentration which carbon implanted in the sixth ALD layer and the seventh ALD layer are higher than a concentration which carbon implanted in the fifth ALD layer, and a concentration which nitrogen implanted in the sixth ALD layer and the seventh ALD layer is higher than a concentration which nitrogen implanted in the fifth ALD layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A semiconductor device, comprising: a plurality of isolation regions, wherein a fin is arranged between two of the plurality of isolation regions, wherein one of the plurality of isolation regions comprises: a first atomic layer deposition (ALD) layer comprising a first trench; a second ALD layer formed in the first trench of the first ALD layer; a flowable chemical vapor deposition (FCVD) layer formed in the first trench of the first ALD layer and on the second ALD layer; and a third ALD layer formed on the FCVD layer.
 2. The semiconductor device of claim 1, wherein the third ALD layer is formed in the first trench of the first ALD layer and on the FCVD layer.
 3. The semiconductor device of claim 2, wherein the third ALD layer is in contact with the second ALD layer and the FCVD layer.
 4. The semiconductor device of claim 1, wherein the first ALD layer comprises a first opening, and the second ALD layer comprises a second opening, wherein the first opening and the second opening are disposed at the same side of the semiconductor device.
 5. The semiconductor device of claim 4, wherein the third ALD layer covers the second opening of the second ALD layer, and the FCVD layer is surrounded by the second ALD layer and the third ALD layer.
 6. The semiconductor device of claim 1, wherein another one of the plurality of isolation regions comprises: a fourth ALD layer comprising a second trench; and a fifth ALD layer formed in the second trench of the fourth ALD layer.
 7. The semiconductor device of claim 6, wherein a width of the one of the plurality of isolation regions is larger than a width of the another one of the plurality of isolation regions.
 8. A semiconductor device, comprising: a first isolation region comprising: a first ALD layer comprising a first trench; a second ALD layer formed in the first trench of the first ALD layer; a FCVD layer formed in the first trench of the first ALD layer and on the second ALD layer; and a deposition layer formed on the second ALD layer and the FCVD layer; a second isolation region comprising: a third ALD layer comprising a second trench; and a fourth ALD layer formed in the second trench of the third ALD layer; and at least one fin is arranged between the first isolation region and the second isolation region.
 9. The semiconductor device of claim 8, wherein the deposition layer is formed in the first trench of the first ALD layer.
 10. The semiconductor device of claim 9, wherein the deposition layer is in contact with the first ALD layer, the second ALD layer, and the FCVD layer.
 11. The semiconductor device of claim 8, wherein the deposition layer comprises an ALD layer, and the FCVD layer is surrounded by the second ALD layer and the deposition layer.
 12. The semiconductor device of claim 11, wherein the second isolation region comprises: a fifth ALD layer formed in the second trench and on the fourth ALD layer.
 13. The semiconductor device of claim 8, wherein the deposition layer comprises a FCVD layer.
 14. The semiconductor device of claim 13, wherein the deposition layer is implanted with impurity, wherein the impurity is distributed in the deposition layer in a gauss manner.
 15. The semiconductor device of claim 14, wherein a number of the at least one fin comprises plural, and the semiconductor device further comprises: a void formed between two fins which are adjacent to each other.
 16. A semiconductor device, comprising: a plurality of fins; a plurality of isolation regions, wherein each of the plurality of isolation regions is formed between two of the plurality of fins being adjacent to each other, wherein a first isolation region of the plurality of isolation regions comprises: a first ALD layer comprising a first trench; and a second ALD layer, wherein the first trench of the first ALD layer is filled with the second ALD layer; wherein the first ALD layer and the second ALD layer are implanted with carbon and nitrogen, wherein a concentration of carbon implanted in the second ALD layer is higher than a concentration of carbon implanted in the first ALD layer, and a concentration of nitrogen implanted in the second ALD layer is higher than a concentration of nitrogen implanted in the first ALD layer.
 17. The semiconductor device of claim 16, wherein the concentration of carbon implanted in the first ALD layer is about 1-3%, and the concentration of nitrogen implanted in the first ALD layer is about 5-20%.
 18. The semiconductor device of claim 17, wherein the concentration of carbon implanted in the second ALD layer is about 5-15%, and the concentration of nitrogen implanted in the second ALD layer is about 10-30%.
 19. The semiconductor device of claim 16, wherein a second isolation region of the plurality of isolation regions comprises: a third ALD layer comprising a second trench; a fourth ALD layer formed in the second trench of the third ALD layer; and a first FCVD layer formed in the second trench of the third ALD layer and on the fourth ALD layer; wherein the third ALD layer and the fourth ALD layer are implanted with carbon and nitrogen, wherein a concentration of carbon implanted in the fourth ALD layer is higher than a concentration of carbon implanted in the third ALD layer, and a concentration of nitrogen implanted in the fourth ALD layer is higher than a concentration of nitrogen implanted in the third ALD layer.
 20. The semiconductor device of claim 19, wherein a third isolation region of the plurality of isolation regions comprises: a fifth ALD layer comprising a third trench; a sixth ALD layer formed in the third trench of the fifth ALD layer, wherein the sixth ALD layer comprises a fourth trench; a second FCVD layer formed in the fourth trench of the sixth ALD layer; and a seventh ALD layer formed on the second FCVD layer; wherein the fifth ALD layer, the sixth ALD layer, and the seventh ALD layer are implanted with carbon and nitrogen, wherein a concentration of carbon implanted in the sixth ALD layer and the seventh ALD layer are higher than a concentration of carbon implanted in the fifth ALD layer, and a concentration of nitrogen implanted in the sixth ALD layer and the seventh ALD layer is higher than a concentration of nitrogen implanted in the fifth ALD layer. 